The following Timing Diagram shows how each Pin tied to an LED is advanced on each rising edge of the clock cycle set by the 555 timing component. The variable resistor VR1 allows for us to change the timer's frequency and speed up or slow the advancing edge.

Each output is normally logic "0" and go logic "1" only at their respective time slot. Each output will remain high for 1 full clock cycle.

At the end of the cycle, the counter is cleared only by a logic "1" at the Reset line.